FPGA/ASIC Developer (medior/senior) - Hilversum


  • Aimvalley
  • HBO of hoger
  • Medior/Senior niveau
  • Vast contract
  • 40 uur
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Functieomschrijving FPGA/ASIC Developer (medior/senior)

AimValley, what we do
With almost 100 colleagues we provide Design Services dedicated to the development of complex embedded systems for telecom applications and other high tech applications. We offer our customers cost-optimal and
energy-efficient products with a very high availability, a long lifetime and the ability to perform in harsh environments. AimValley has a strong track record in development of such products.

AimValley, organizational culture
At AimValley we have an open and direct culture. We are technology driven. Developers focus on “getting things done”. We have short lines of communication and there is ample room for autonomy, driven by professionalism. Teamwork is key to our success. Teams are grouped around a customer project and work systematically to provide the required features and the agreed time to market. We pride ourselves in delivering our projects on time and on budget.

Why work for AimValley as an FPGA/ASIC Developer
  • High End FPGA/ASIC Products.
  • Challenging work environment in design of complex products.
  • One of the top places in FPGA/ASIC design in The Netherlands.
  • A good Work/Life balance by flexible working hours (between 7 am and 7 pm) and a possibility to work up to 70% part-time and work remotely.
  • Excellent team spirit.
  • Occasional travel to customers (also abroad).
  • Opportunity for personal growth in technical and managerial areas.
The Job
  • Development of high speed digital data processing blocks for FPGA or ASIC.
  • Requirement definition from high level specifications.
  • Definition of verification and evaluation plans.
  • Performance of simulations/verifications/testing on building blocks and complete designs.
  • Creation of design and verification documentation.
  • Project planning according to agreed deliverables.
  • Integration of IP, like Serdes/DDR interfaces/DSP/Soft cores.

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Functie-eisen Requirements
  • Minimum BS (Ing.) in Electrical or Computer Engineering.
  • Minimum of 5 years relevant FPGA design experience.
  • Ability to think and act outside your own domain (electronics & embedded).
  • Ability to lead informally.
  • Ability to have a system overview.
Hard skills
  • Expertise in RTL coding in VHDL.
  • Expertise in FPGA tools (Vivado, Quartus).
  • Expertise with simulation tools (Modelsim).
  • Expertise with script languages (Tcl/Tk , Pearl, Python).
  • Experience with SystemVerilog.
  • Experience with FPGA Acceleration Tooling and HLS (Vitis).
  • Project Management.
  • Quality Conscience.
Soft skills
  • Team player mentality.
  • Organized/Task Driven.
  • Great communicator.
  • Can-Do mentality.
  • Flexible.
Nice to have:
  • Ability to deal with electronics and measurement equipment in a laboratory.
Knowledge of
  • Telecommunication protocols (Ethernet, SDH, SONET, OTN, PON).
  • Interconnect protocols (PCIe, SPI, I2C, AMBA, AXI)
  • ASIC design process and tooling.
  • Experience with power aware design and verification.
  • Experience with UVM verification techniques.
  • English literate.
  • Dutch literate or willingness to learn Dutch.
  • Willingness to travel and work occasionally at the customer site.
  • Willingness to work outside normal working hours occasionally if required for the project.
More information and/or your application
For this please contact Dick Brons via 06 348 19 201 and/or mail dwb(at)bronsconsulting(dot)nl. Or apply via the application button.

Agency calls are not appreciated.

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Taalvaardigheid Vereist: Nederlands
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